1. Field of the Invention
The present invention generally relates to high density integrated circuits and, more particularly, to manufacture of field-effect transistors (FETs) at very small size regimes.
2. Description of the Prior Art
Performance and economic factors of integrated circuit design and manufacture have caused the scale of elements (e.g. transistors, capacitors and the like) of integrated circuits to be drastically reduced in size and increased in proximity on a chip. That is, increased integration density and proximity of elements reduces the signal propagation path length and reduces signal propagation time and susceptibility to noise and increase of possible clock rates while the reduction in element size necessary for increased integration density increases the ratio of functionality which can be provided on a chip (approaching, if not achieving, a “system on a chip”) to the costs of production (e.g. wafer/chip area and process materials) per chip and, potentially, the cost of devices containing the chips by reducing the number of inter-chip and inter-board connections required in a complete apparatus.
Complementary field effect transistors, sometimes referred to as CMOS, have become the switching device technology of choice for all but the highest frequency designs of high density integrated circuits due to extremely low current drive requirements (which diminish at small size regimes since the load represented by the input is substantially capacitive) and other convenient and desirable properties. In this technology, field-effect transistors (FETs) of complementary conductivity type are used in pairs (e.g. a series connection of a pFET and an nFET having a common input) to obtain a complementary and, preferably substantially symmetric switching function. However, to obtain a reasonable degree of symmetry, generally similar electrical properties must be developed in the complementary transistors forming each pair of transistors notwithstanding the different semiconductor conductivity types and majority charge carriers therein.
At extremely small size regimes currently and foreseeably of interest (e.g. about 60 nm channel length and smaller), performance of FETs is often degraded by so-called short channel effects unless special structures such as extension and/or halo implants are employed to maintain acceptable levels of performance. However, the difference in physical behavior of dopants for semiconductors used to produce different conductivity types of transistors presents substantial difficulties in manufacture of FETs, particularly including such structures having acceptable electrical performance at acceptable manufacturing yields. In particular, boron is generally used for extension and source/drain implants in pFETs and in halo implants in nFETs (sometimes with indium) while arsenic (and/or phosphorus) is used for the extension and source/drain implant structures in nFETs and halo implants in pFETs. While arsenic diffuses sufficiently slowly in silicon at annealing temperatures to allow shallow and abrupt junctions to be maintained at the source, and drain of nFETs, boron diffuses at a much faster rate at the same temperatures. The faster diffusion rate of boron causes the tip of the impurity region of extension implants to spread under the transistor gate, shortening the channel further and increasing the junction depth within the silicon, compromising a shallow channel geometry that allows the channel conductivity to be suitably controlled at low gate threshold voltages. Therefore, there is a trade-off between low resistance extensions and source/drain regions which require a high temperature activation annealing process and shallow junctions to maintain suitable switching thresholds and avoid undesirable rolloff effects (e.g. a reduction of switching threshold with reduction of channel length) which can lead to unacceptably low switching thresholds at short channel lengths.
It is known in the art to provide halo implants (e.g. counter doping of the opposite impurity type below the source/drain and extension implant regions) to partially offset poor rolloff characteristics. However, halo implants require substantial process complexity while degrading carrier mobility and transistor reliability. Further, the high diffusivity of boron prevents use of extremely narrow spacers for self-aligned source/drain implants which are important to maintaining a low external resistance for the transistor while a larger spacer also tends to increase overall size of the transistor.
More specifically, current microprocessor and “system on a chip” designs require devices to be made without silicide on source, drain or gate regions. Suitable processes are sometimes referred to as OP processes in which a hard mask of, for example, silicon nitride, is patterned and used to block formation of silicide or salicide. High performance circuits also require high temperature annealing to activate junctions. During such an anneal, boron will diffuse over substantial distances sufficient to substantially degrade transistor performance.
It is also known that the diffusivity of boron in silicon can be reduced by application of a high compressive force thereto. However, mechanical application of stress levels sufficient to significantly affect diffusivity of boron in silicon is difficult to achieve or regulate and may cause damage such as cracking to the wafer. Further, compressive force in the channel region of an nFET is known to reduce electron mobility and compromise device performance if not removed as the transistor is completed. The same is true of tensile force (which may result from compressive force applied elsewhere on the chip or wafer) in regard to hole mobility in pFETs.
It is known to apply compressive force to individual devices on silicon chips by deposition of a material on a surface or in a trench surrounding the device and then reducing the volume of the deposited material as disclosed in U.S. Pat. Nos. 6,069,049 and 6,399,976 which are assigned to the assignee of the present invention and fully incorporated by reference herein. However, the force developed in accordance with this technique is persistent and the structure is intended to remain in the completed chip to avoid propagation of crystal lattice defects. The forces produced in this manner may not be suitable in magnitude or location for reduction of boron diffusivity. In particular, the location of forces produced in this manner is not compatible with fabrication of high performance logic transistors, since high performance CMOS does not utilize capacitors in memory cells or random logic circuitry.
Additionally, junction capacitance (Cj) is a major parasitic element which arises from the depletion charge between the source/drain implant and the oppositely doped substrate which contributes to switching delay in CMOS circuits and is a significant part of the output capacitance in bulk CMOS circuits. Limitation of junction capacitance has been approached through use of expensive silicon-on-insulator structures which have an inherently lower junction capacitance than bulk FETs. In bulk FETs, implants have been used to reduce junction capacitance by developing graded junctions. However, at particularly small feature size regimes, boron diffusivity in the horizontal direction increases process parameter criticality in nFETs where boron is used (sometimes with indium) for the halo implants. In pFETs, lateral diffusion of the source/drain implants can reduce the perimeter component of junction capacitance by compensating the halo implant, thereby eliminating the p-n junction between the source/drain and the halo which reduces the overall junction capacitance. However, excessive boron diffusion in the vertical direction can lead to an increase in the area component of junction capacitance. Thus, if the lateral diffusion of boron in the source/drain region can be increased without causing increased overlap capacitance and, simultaneously, the vertical diffusion of boron in the source/drain region can be minimized, then junction capacitance can be significantly reduced. The increase in junction capacitance with increased compressive forces from shallow trench isolation (STI) structures has been reported and attributed to change in band gap in “Stress-Induced Increase in Reverse Bias Junction Capacitance” by V. P. Gopinath et al., IEEE Electron Device Letters, Vol. 23, No. 6, June 2002. This effect is not considered to be fully understood but could possibly be explained by either stress-induced alteration of vertical diffusion of impurities or stress induced band gap change with compressive force as the author of the article proposes or a combination thereof. In any case, the use of STI or other structures providing a compressive force across transistors for the purpose of reducing boron diffusivity compromises transistor performance by increasing junction capacitance.
Another component of parasitic capacitance which may degrade FET switching speed is referred to as overlap capacitance (Cov) which is basically the capacitance between the gate electrode and the extension implants in the area where the former overlaps the latter. As can be readily appreciated in view of the above discussion, overlap capacitance is increased by the increased distance of boron diffusion in pFETs.